91 lines
3.7 KiB
C
91 lines
3.7 KiB
C
/*
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* Copyright (c) 2020 Huawei Technologies Co.,Ltd.
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*
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* openGauss is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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*
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* http://license.coscl.org.cn/MulanPSL2
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*
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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* ---------------------------------------------------------------------------------------
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*
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* atomic_arm.h
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* Assembly implementation of 128bit exclusive CAS and atomic operations
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* leverage ARMv8.1-a large system extension(LSE), which is faster than
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* legacy exclusive mode APIs of GNU Built-in functions.
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* Create on: 2020-01-11
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*
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*
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* IDENTIFICATION
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* src/include/utils/atomic_arm.h
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*
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* ---------------------------------------------------------------------------------------
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*/
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#ifndef ATOMIC_ARM_H
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#define ATOMIC_ARM_H
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#include "c.h"
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#include "elog.h"
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#ifdef __aarch64__
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/*
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* Exclusive load/store 2 uint64_t variables to fullfil 128bit atomic compare and swap
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* */
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static inline uint128_u __excl_compare_and_swap_u128(volatile uint128_u *ptr, uint128_u oldval, uint128_u newval)
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{
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uint64_t tmp, ret;
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uint128_u old;
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asm volatile("1: ldxp %0, %1, %4\n"
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" eor %2, %0, %5\n"
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" eor %3, %1, %6\n"
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" orr %2, %3, %2\n"
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" cbnz %2, 2f\n"
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" stlxp %w2, %7, %8, %4\n"
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" cbnz %w2, 1b\n"
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" b 3f\n"
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"2:"
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" stlxp %w2, %0, %1, %4\n"
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" cbnz %w2, 1b\n"
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"3:"
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" dmb ish\n"
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: "=&r"(old.u64[0]), "=&r"(old.u64[1]), "=&r"(ret), "=&r"(tmp),
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"+Q"(ptr->u128)
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: "r"(oldval.u64[0]), "r"(oldval.u64[1]), "r"(newval.u64[0]), "r"(newval.u64[1])
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: "memory");
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return old;
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}
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/*
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* using CASP instinct to atomically compare and swap 2 uint64_t variables to fullfil
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* 128bit atomic compare and swap
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* */
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static inline uint128_u __lse_compare_and_swap_u128(volatile uint128_u *ptr, uint128_u oldval, uint128_u newval)
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{ \
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uint128_u old; \
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register unsigned long x0 asm ("x0") = oldval.u64[0]; \
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register unsigned long x1 asm ("x1") = oldval.u64[1]; \
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register unsigned long x2 asm ("x2") = newval.u64[0]; \
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register unsigned long x3 asm ("x3") = newval.u64[1]; \
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\
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asm volatile(".arch_extension lse\n" \
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" caspal %[old_low], %[old_high], %[new_low], %[new_high], %[v]\n" \
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: [old_low] "+&r" (x0), [old_high] "+&r" (x1), \
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[v] "+Q" (*(ptr)) \
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: [new_low] "r" (x2), [new_high] "r" (x3) \
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: "x30", "memory"); \
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\
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old.u64[0] = x0; \
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old.u64[1] = x1; \
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return old;
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}
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#endif /* __aarch64__ */
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#endif
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