BUGFIX: fix error log of write throttle
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@ -336,13 +336,7 @@ void ObFifoArena::advance_clock()
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int64_t trigger_percentage = get_writing_throttling_trigger_percentage_();
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int64_t trigger_mem_limit = lastest_memstore_threshold_ * trigger_percentage / 100;
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int64_t cur_mem_hold = ATOMIC_LOAD(&hold_);
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bool need_speed_limit = false;
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if (trigger_percentage < 100) {
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need_speed_limit = cur_mem_hold > trigger_mem_limit;
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}
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int64_t mem_limit =
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(need_speed_limit ? calc_mem_limit(cur_mem_hold, trigger_mem_limit, ADVANCE_CLOCK_INTERVAL) :
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trigger_mem_limit - cur_mem_hold);
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int64_t mem_limit = calc_mem_limit(cur_mem_hold, trigger_mem_limit, ADVANCE_CLOCK_INTERVAL);
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int64_t clock = ATOMIC_LOAD(&clock_);
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int64_t max_seq = ATOMIC_LOAD(&max_seq_);
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ATOMIC_SET(&clock_, min(max_seq, clock + mem_limit));
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@ -361,7 +355,11 @@ int64_t ObFifoArena::expected_wait_time(const int64_t seq) const
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int64_t can_assign_in_next_period = calc_mem_limit(hold_, trigger_mem_limit, ADVANCE_CLOCK_INTERVAL);
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int64_t clock = ATOMIC_LOAD(&clock_);
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if (seq > clock) {
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expected_wait_time = (seq - clock) * ADVANCE_CLOCK_INTERVAL / can_assign_in_next_period;
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if (can_assign_in_next_period != 0) {
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expected_wait_time = (seq - clock) * ADVANCE_CLOCK_INTERVAL / can_assign_in_next_period;
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} else {
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expected_wait_time = ADVANCE_CLOCK_INTERVAL;
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}
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}
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return expected_wait_time;
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}
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@ -372,44 +370,54 @@ int64_t ObFifoArena::calc_mem_limit(const int64_t cur_mem_hold, const int64_t tr
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int ret = OB_SUCCESS;
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int64_t mem_can_be_assigned = 0;
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int64_t init_seq = ((cur_mem_hold - trigger_mem_limit) + MEM_SLICE_SIZE - 1) / (MEM_SLICE_SIZE);
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int64_t init_page_left_size = MEM_SLICE_SIZE - (cur_mem_hold - trigger_mem_limit) % MEM_SLICE_SIZE;
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double init_page_left_interval = (1.0 * throttle_info_.decay_factor_ * pow(init_seq, 3) *
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init_page_left_size / MEM_SLICE_SIZE);
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double past_interval = throttle_info_.decay_factor_ * pow(init_seq, 2) * pow(init_seq + 1, 2) / 4;
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int64_t init_seq = 0;
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int64_t init_page_left_size = 0;
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double init_page_left_interval = 0;
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double past_interval = 0;
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double last_page_interval = 0;
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double mid_result = 0;
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double approx_max_chunk_seq = 0;
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int64_t max_seq = 0;
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double accumulate_interval = 0;
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if (init_page_left_interval > dt) {
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last_page_interval = throttle_info_.decay_factor_ * pow(init_seq, 3);
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mem_can_be_assigned = dt / last_page_interval * MEM_SLICE_SIZE;
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if (cur_mem_hold < trigger_mem_limit) {
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// there is no speed limit now
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// we can get all the memory before speed limit
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mem_can_be_assigned = trigger_mem_limit - cur_mem_hold;
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} else {
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mid_result = 4.0 * (dt + past_interval - init_page_left_interval) / throttle_info_.decay_factor_;
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approx_max_chunk_seq = pow(mid_result, 0.25);
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max_seq = floor(approx_max_chunk_seq);
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for (int i = 0; i < 2; i++) {
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if (pow(max_seq, 2) * pow(max_seq + 1, 2) < mid_result) {
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max_seq = max_seq + 1;
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init_seq = ((cur_mem_hold - trigger_mem_limit) + MEM_SLICE_SIZE - 1) / (MEM_SLICE_SIZE);
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init_page_left_size = MEM_SLICE_SIZE - (cur_mem_hold - trigger_mem_limit) % MEM_SLICE_SIZE;
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init_page_left_interval = (1.0 * throttle_info_.decay_factor_ * pow(init_seq, 3) *
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init_page_left_size / MEM_SLICE_SIZE);
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past_interval = throttle_info_.decay_factor_ * pow(init_seq, 2) * pow(init_seq + 1, 2) / 4;
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// there is speed limit
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if (init_page_left_interval > dt) {
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last_page_interval = throttle_info_.decay_factor_ * pow(init_seq, 3);
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mem_can_be_assigned = dt / last_page_interval * MEM_SLICE_SIZE;
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} else {
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mid_result = 4.0 * (dt + past_interval - init_page_left_interval) / throttle_info_.decay_factor_;
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approx_max_chunk_seq = pow(mid_result, 0.25);
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max_seq = floor(approx_max_chunk_seq);
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for (int i = 0; i < 2; i++) {
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if (pow(max_seq, 2) * pow(max_seq + 1, 2) < mid_result) {
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max_seq = max_seq + 1;
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}
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}
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accumulate_interval = pow(max_seq, 2) * pow(max_seq + 1, 2) * throttle_info_.decay_factor_ / 4 - past_interval + init_page_left_interval;
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mem_can_be_assigned = init_page_left_size + (max_seq - init_seq) * MEM_SLICE_SIZE;
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if (accumulate_interval > dt) {
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last_page_interval = throttle_info_.decay_factor_ * pow(max_seq, 3);
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mem_can_be_assigned -= (accumulate_interval - dt) / last_page_interval * MEM_SLICE_SIZE;
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}
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}
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accumulate_interval = pow(max_seq, 2) * pow(max_seq + 1, 2) * throttle_info_.decay_factor_ / 4 - past_interval + init_page_left_interval;
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mem_can_be_assigned = init_page_left_size + (max_seq - init_seq) * MEM_SLICE_SIZE;
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if (accumulate_interval > dt) {
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last_page_interval = throttle_info_.decay_factor_ * pow(max_seq, 3);
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mem_can_be_assigned -= (accumulate_interval - dt) / last_page_interval * MEM_SLICE_SIZE;
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// defensive code
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if (pow(max_seq, 2) * pow(max_seq + 1, 2) < mid_result) {
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LOG_ERROR("unexpected result", K(max_seq), K(mid_result));
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}
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}
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// defensive code
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if (pow(max_seq, 2) * pow(max_seq + 1, 2) < mid_result) {
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LOG_ERROR("unexpected result", K(max_seq), K(mid_result));
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if (mem_can_be_assigned == 0) {
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LOG_WARN("we can not get memory now", K(mem_can_be_assigned), K(throttle_info_.decay_factor_), K(cur_mem_hold), K(trigger_mem_limit), K(dt));
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}
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if (cur_mem_hold < trigger_mem_limit) {
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LOG_ERROR("we should not limit speed now", K(cur_mem_hold), K(trigger_mem_limit));
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}
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return mem_can_be_assigned;
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}
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